A VME device that can act as a bus master can perform DMA into memory. The general sequence of operations in this case is as follows:
Software in the Silicon Graphics CPU uses PIO to program the device registers of the VME device, instructing it to perform DMA to a certain VME bus address for a specified length of data.
The VME bus master initiates the first read, write, block-read, or block-write cycle on the VME bus.
The VME controller, responding as a slave device on the VME bus, recognizes the VME bus address as one that corresponds to a physical memory address in the system.
If the bus master is writing, the VME controller accepts the data and initiates a system bus cycle to write the data to system memory.
If the bus master is reading, the VME controller uses a system bus cycle to read data from system memory, and returns the data to the bus master.
The bus master device continues to use the VME controller as a slave device until it has completed the DMA transfer.
During a DMA transaction, the VME bus controller operates independently of any CPU. CPUs in the system execute software concurrently with the data transfer. Since the system bus is faster than the VME bus, the data transfer takes place at the maximum data rate that the VME bus master can sustain.